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An alternative solution is to use slotted S-CPW. Since the shield is a good conductor, there is no electric field tangential to the strips and thus the voltage on the shield is zero with respect to CPW and hence can provide a better shield than GCPW [59].

Using slotted strips under the CPW increases the effective C without impacting the inductance significantly.

To validate the phenomenon, the slotted S-CPW is designed using the top thickest metal M9 with slots on the next metal layer M8. Figure 3 - 5 shows simulation results of the insertion loss as well as quality factor of the structures. Figure 3 - 6 shows chip micrographs of single-stage and quad-core-coupled TPVs. All passive components are simulated using Sonnet 3D electromagnetic EM simulator.

Figure 3 - 7 shows the test setup used for the measurements. The LO is provided using an Agilent EA PSA spectrum analyser with an added capability to map the downconverted signal back to its original frequency. The output power is measured using Erickson PM4 power meter. Table 3 - 1 summarizes the measurement results for the different flavours of the implemented structure.

As can be seen from the table, the slow-wave TPV has the best performance, with 2. The advantage of using a quad-core-coupled architecture is also apparent. Figure 3 - 8 a shows the captured GHz signal note that the spectrum analyser has mapped the downconverted IF signal back to the RF band. Figure 3 - 8 b shows output power and tuning range of the proposed prototype.

Introduction to CMOS low power design

Table 3 - 2 summarizes the performance of the proposed slow-wave TPV prototype and includes the performance of the related state-of-the-art designs for the purpose of comparison. The proposed design compares favourably with the state-of-the-art and achieves 2. The structure uses S-CPW to increase the quality factor of the fundamental tank and the combiner, and four cores coupled together to increase the output power.

The measurement results show S-CPW-based design achieves 2. The performance of the proposed designs compares favorably with that of the state-of-the-art. However, as mentioned in previous chapter and to remind efficient power generation at these high frequencies in bulk CMOS processes faces daunting challenges on several fronts: 1 such frequencies are near or above the unity power gain frequency, fmax, of the transistors, 2 high-frequency loss mechanisms such as substrate loss, skin and proximity effects deteriorate the quality factor of passive components, and 3 CMOS scaling, though increasing the fmax of MOS transistors, reduces the maximum tolerable signal swing due to lower supply voltage VDD.

To overcome the limited power gain of the device in CMOS technology, device nonlinearity is usually utilized to generate power around the harmonic components. Signal sources based on harmonic power extraction leverage either harmonic oscillators or frequency-multipliers. Harmonic oscillators, shown in Figure 4 - 2 a , contain active device s M1 that are simultaneously responsible for providing the power to sustain the oscillation at the 2 This chapter is written collaboratively and the results are published in [].

Amir Nikpaik is the first author of this paper and I am the second author. The feedback network for oscillation at f0 is represented by the Y-parameter matrix, [Yp], and the harmonic output at nf0 is extracted from the output with a matching network tuned at nf0. For example, a 2f0 component can be extracted at the center-tap of a push-push cross-coupled oscillator [3] using a matching network tuned at 2f0, or a 3f0 component can be extracted from a triple-push oscillator[17],.

A frequency-multiplier-based source Figure 4 - 2 b , on the other hand, uses an active device M1 for sustaining oscillation only at f0, and uses another active device M2 as a non-linear harmonic extractor to give the desired output at nf0. Recent examples of CMOS frequency-multipliers, without integrated fundamental sources, have achieved high output power and high harmonic efficiencies[64]—[66]. In this chapter, we discuss and compare challenges to design high-efficiency sub- THz sources in bulk CMOS processes for each of the above-mentioned method.

Optimum conditions to efficiently extract harmonic power near or above fmax from a MOS transistor are described in Section II, and then impediments to fulfill such conditions for harmonic oscillators are explained in Section III. Next, a 51 to GHz multiplier-based source with 2.

Implemented in a nm CMOS process, in the proposed architecture, four fundamental oscillator cores are injection-locked in-phase together at f0. Each fundamental oscillator drives a class-C frequency doubler. The output power of these four doublers are combined and matched to the output. Section VI presents the measurement results for the proposed source and compares its performance with other state-of-the-art CMOS oscillators.

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In harmonic oscillators Figure 4 - 2 a , there is no external load e. As voltage swings approach VDD, the active device enters the deep triode region, internal loss increases, P1 decreases, and eventually, in the steady-state, P1 equals Ppassive. Assuming that the passive circuit is linear, Ppassive increases quadratically with the voltage swing. Thus, if the optimum conditions for fundamental power generation are fulfilled, the oscillation sustains at higher voltage swings and hence generates more harmonic power.

In other words, in harmonic oscillators, optimum condition for fundamental power generation is necessary, but not sufficient, condition to maximize the harmonic power. Also, the impacts of Rsb and Csb are neglected. Equation 8 presents a simple expression to design the passive network, where the parameters in the right hand side of 8 can be readily obtained using a DC operating point simulation. As Ag increases, Pout,max increases first. But beyond a certain threshold, as Ag increases, the transistor operates in the triode region for greater portion of the oscillation period, the effective Gm degrades, the effective GDS increases and hence Pout,max drops.

Pout,max also degrades with increase in frequency because the power dissipation at the gate due to RG and at the extrinsic part of the transistor due to Rdb and Rbb rises quadratically with the frequency. Therefore, careful layout of the transistor is important to minimize RG. When operating as a push-push oscillator, the resonance circuit not shown attenuates higher voltage harmonics so that vg t and vd t of the transistors can be approximated with their fundamental components.

At a specific harmonic, a transistor operating under large-signal time-varying regime may be modeled by an equivalent circuit3 [69]. For the range of frequencies of our interest, nf0 falls near or above the device fmax, and therefore the above approximation usually provides an acceptable estimation for Pav,n. In general, Is,n and Gs,n are functions of the gate signal waveform vg t and the drain signal waveform vd t. Both Is,n and Gs,n can be calculated using harmonic balance simulations. In this Section, we first consider a push-push oscillator, and then extend our discussion to a generic harmonic oscillator.

Therefore, the 56 necessary condition for efficient harmonic extraction is not fulfilled. On the other hand, the second harmonic power generated at the drain node is partially dissipated at the gate resistance RG , because the drain node is cross-connected to the gate of the transistor pair. Moreover, in push-push architectures, the device transconductance Gm affects Gs,2. Indeed, at even harmonics, each transistor in the cross-coupled pair can be considered as a diode-connected device. In other words, there is a fundamental trade-off between power generation at the fundamental and at a higher harmonic frequency.

An elegant solution to mitigate the impact of Gm is proposed in [69] self-feeding oscillator where the feedback between the gate and drain nodes at 2f0 is broken by exploiting a quarter-wavelength transmission line T-line. Although the impact of Gm on Gs,2 is alleviated in self-feeding oscillator, the gate node still experiences harmonic voltage component at 2f0 leading to harmonic loss at the gate due to RG.

More importantly, due to the large fundamental voltage swing at the drain node, the influence of GDS on Gs,2 still persists.

Special order items

To achieve the desired power level at such high frequencies, typically, the harmonic power generated at different oscillator cores are combined. For example, consider a push-push or n-push structure. Due to the impedance mismatch at node C in Figure 4 - 7, multiple reflections occur which significantly adds loss to the harmonic signal [71]. As an example, in the design proposed in [64], the second harmonic power generated at the drain of each transistor at about GHz should traverse 1. In an optimum design, to avoid this loss, harmonic power combining should take place right beside the transistor.

The Design of CMOS Radio-Frequency Integrated Circuits

Optimum Harmonic Oscillator to Extract 2f0 Consider a simulation setup similar to Figure 4 - 6 a for the generic harmonic oscillator of Figure 4 - 2 a. If a perfect harmonic isolation is hypothetically assumed between gate and drain terminals, no second harmonic power is dissipated at the gate. Figure 4 - 8 c also shows the fundamental trade-off between the fundamental power generation and the harmonic power generation for the generic harmonic oscillator.

As shown in Figure 4 - 8 c , the harmonic power efficiency keeps increasing as Ag and Ad increase. On the other hand, the fundamental power P1 is maximized at a completely different point and the direction of its variation is also totally different from that of the harmonic power. If a wider transistor is used to increase P1 and the oscillation amplitude, to keep the oscillation frequency constant, inevitably, a smaller tank inductance should be used. The biggest limitation for harmonic oscillators is the fact that a single transistor simultaneously generates harmonic power and restores fundamental passive loss.

Consider the generic multiplier-based source shown in Figure 4 - 2 b , where M2 is used for frequency multiplication. As the drain node of M2 does not necessarily experience high swing at f0, M2 can operate without being pushed into the triode region for large voltage swings at the gate node, and hence Gs,2 does not degrade.

Besides, in comparison to a cross-coupled pair, there is neither a negative feedback from the drain to the gate, nor any harmonic power that is being dissipated at the gate. Furthermore, unlike harmonic oscillators, where both the fundamental power at f0 and the harmonic power at 2f0 generated at the drain of the transistor suffers from the loss of the T-line in the core oscillator tank see Figure 4 - 7 , only the fundamental power at f0 suffers from such loss here.

6 editions of this work

Therefore, a transistor employed in a multiplier can more efficiently extract harmonic power as compared to a transistor used in a harmonic oscillator. Next, we quantitatively compare the maximum achievable harmonic power efficiency of the CMOS multiplier-based source to that of the harmonic oscillator.

The drain terminal is simply connected to the supply voltage. In these simulations, the drain node of M2 does not see any fundamental swing. The next step is designing a fundamental oscillator to drive the doubler.

The fundamental oscillator should deliver 0. In general, passive circuits embedding the transistor s determine the above-mentioned conditions. The fundamental oscillator consumes 2. Repeating the above procedure for other transistors and harmonic power levels results in a similar conclusion. In case of multiplier-based sources, the presence of the second harmonic components will improve the fundamental power generation efficiency of the core oscillator as well as the harmonic power generation efficiency of the doubler. Thus, the conclusion remains valid even if the impact of the second harmonic components is taken into account.

The oscillator core at the fundamental frequency is designed using the procedure presented in Section IV. It should be noted that the TLC lines are part of resonator and affect the oscillation frequency. This passive coupling scheme does not dissipate additional DC power, and is therefore attractive for overall efficiency. The output of each core feeds an active doubler designed to efficiently extract the second harmonic 2f0 power by operating in class-C mode.